The present invention pertains to a software development system and more particularly to an arrangement for interrupting the normal operation of a processor for testing purposes.
A basic feature of any software development system is the ability to temporarily stop the processing of a central processing unit (breakpoint) upon the occurrence of a particular software event. One method of accomplishing a breakpoint is to actually modify the program instructions in memory such that, when the desired location in memory has been reached, a halt or an interrupt instruction is encountered in order to freeze the execution of the program at that point.
This method can only detect instruction execution. It cannot detect an access of a certain data word in memory or the access of a particular input/output port. This is the chief shortcoming of such software breakpoints.
Detecting memory data word access or input/output port access is best accomplished by a hardware matcher. A hardware matcher is a device which monitors the address and data busses of a system and compares the bit pattern present for an access to these busses with a predefined bit pattern in order to generate an indication of a comparison match.
One method of implementing a hardware matcher is with exclusive-OR gates or magnitude comparators. Since exclusive-OR gates and comparator devices are typically packaged to handle four bits per chip, matchers which employ these devices must be greatly expanded to accommodate the large bus sizes of modern processing systems. Due to the great number of chips required in such a configuration, excess power consumption and thermal radiation occur. In addition, problems of signal propagation delay through gates are observed. Further, a large amount of components requires a large amount of physical space.
Therefore, these approaches are impractical when used with new generation of microprocessors, which have increasingly large address and data bus capabilities.